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The Intel MCS-96 is a family of microcontrollers (MCU) commonly used in embedded systems. The family is often referred to as the 8xC196 family, or 80196, the most popular MCU in the family. These MCUs are commonly used in hard disk drives, modems, printers, pattern recognition and motor control. In 2007, Intel announced the discontinuance of the entire MCS-96 family of microcontrollers. Intel noted that "There are no direct replacements for these components and a redesign will most likely be necessary."〔http://www.intel.com/design/support/faq/microcontrollers/96_components.htm〕 == History == The MCS-96 family originated as a commercial derivative of the Intel 8061, the first processor in the Ford EEC-IV engine controller family. Differences between the 8061 and the 8096 include the memory interface bus, the 8061's M-Bus being a 'burst-mode' bus requiring a tracking program counter in the memory devices. There were also considerable differences in the I/O peripherals of the two parts – the 8061 had 8 HSI (pulse-measurement) inputs, 10 HSO (pulse-generation) outputs entirely separated from the HSI pins, and a non-sampling 10-bit ADC with more channels than the 8096 had. Many differences between the EEC-IV and the 8096 resulted from an effort to share pins to reduce I/O pin count in favor of using the pins for a more conventional memory interface bus. The 8096 also had on-chip program memory lacking in the 8061. Ford created the Ford Microelectronics facility in Colorado Springs in 1982 to propagate the EEC-IV family, develop other custom circuits for use in automobiles, and to explore the gallium arsenide integrated circuit market. Parts in that family included the 8065, which incorporated a memory controller allowing it to address a megabyte of memory. The family of microcontrollers are 16-bit, however they do have some 32-bit operations. The processors operate at 16, 20, 25, and 50 MHz, and is separated into 3 smaller families. The HSI (high speed input) / HSO (high speed output) family operates at 16 and 20 MHz, and the EPA (event processor array) family operates at all of the frequencies. The main features of the MSC 96 family include a large on-chip memory, Register-to-register architecture, three operand instructions, bus controller to allow 8 or 16 bit bus widths, and direct flat addressability of large blocks (256 or more) of registers. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Intel MCS-96」の詳細全文を読む スポンサード リンク
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